Andy Geppert's SAO Core4 Adds Nostalgic Four-Bit Memory Tech to Modern Conference Badges

Core memory is an electronic data storage technology from the Apollo space program. Despite its age, it is relatively straightforward to implement with modern materials. Andy Geppert took advantage of this point when creating the conference badge add-on, SAO Core4, a four-bit (nibble) core memory module.

Core4 is an authentic four-bit core memory device. Its circuit board measures approximately 50 by 64 millimeters. The board's center contains "sockets" to accommodate four wound ferrite cores, backlit LEDs to indicate their status and other support circuits. The SAO header is its primary interface to the outside world and is popular on conference badges. This design features two headers to make chaining multiple SOAs easier.

Core memory stores a single bit of data by magnetizing a ferrite core with one of two polarities. The polarity defines whether the bit represents a binary 0 or binary 1. A sense circuit consisting of differential amplifiers connected to an RS-Latch read a bit. (Geppert used a quad-NOR gate IC to implement the latch.) A driver provides a method to write bits to the matrix (and select one for reading).

Geppert is no stranger to core memory. In the past, he created the Core64 kit and, later, a Core16. As their names imply, these are 64- and 16-bit memory units. Each features core memory bits that you weave to create the memory. However, the SAO Core4's design is less labor-intensive than previous kits and is more friendly to conference badge shenanigans.

SAO Core4 does not do much standalone. The SAO header is ideal for one of the many microcontroller-based conference badges available. The SAO specification is a loosely defined standard for connecting peripherals to conference badges. The physical 2x3 0.1-inch (2.54mm) pitch connector has pins for 3.3 volts, GND, two GPIOs, and I2C. Badges use a socket, while add-ons (peripherals) use pins.

A Microchip MCP23017 I2C IO expander is the key chip to making Core4 compatible with the SOA standard. This IC has 16 general-purpose IO pins, with Core4 using 14 IOs to interact with the matrix. While I2C is the preferred communication method with SOAs and the MCP23017, Geppert says other microprocessors or simpler computers like the Voja4 could bit-bang the port expander.

You can download the work-in-progress KiCad design files from the Core4 GitHub repository. You may also want to watch the Core64.io Shop in case Geppert makes these SAOs available for sale before Supercon 2024. Last, this project page has some additional details about the design.