AMD Spartan™ UltraScale+™ FPGAs: A Look Into the New Cost Optimized Device Family

AMD Spartan™ FPGAs have been a cornerstone in their portfolio for many years now. Well-known for their small packaging, low power, and high I/Os - on top of being the lowest cost — Spartan FPGAs are a common find in many industry products.

They were so popular in fact that when the Spartan architecture evolved from the 45nm technology Spartan 6 FPGA to the 28nm Spartan 7 FPGA in 2017, specific design guides and tutorials were released for the migration from the Spartan 6 FPGA to the Spartan 7 FPGA after part shortages zapped remaining Spartan 6 FPGA stock levels in 2021 and 2022. During that time, I also previously wrote an article that was a deep dive into the differences between the Spartan 6 FPGAs and Spartan 7 FPGAs.

Fast forward to 2025 and now AMD is adding an UltraScale+ version of the Spartan FPGA to their portfolio of adaptive SoCs and FPGAs. While the Spartan 7 FPGA was optimized from the Spartan 6 FPGA, the Spartan UltraScale+ FPGA is an additional offering alongside the Spartan 7 FPGA to expand the breadth of the cost optimized portfolio.

AMD UltraScale™ vs UltraScale+™ vs 7 Series architecture

Before I get into the details of the new AMD Spartan UltraScale+™ FPGAs and how it compares to previous generation devices, let me provide some additional context to the AMD cost optimized portfolio. For those that are not familiar, AMD FPGAs are available in two main families: 7 Series architecture and UltraScale architecture. Then there are four main variations within those three main architecture types: AMD Spartan devices, AMD Artix™ devices, AMD Kintex™ devices, and AMD Virtex™ devices.

The main differences between the families are the amount of programmable logic, I/O pins, and package sizes each offers, where the Spartan FPGAs start at the low-end of the spectrum, offering the smallest package with lowest power consumption. Then the families step up through the AMD Artix devices, Kintex devices, and finally to the Virtex devices, which are on the opposite end of the spectrum, offering the most optimized performance for speed and maximum amount of I/O pins.

So to give a bit more perspective on where this latest release fits in the AMD FPGA portfolio: Spartan FPGAs were the only FPGA family that wasn't available in the UltraScale/UltraScale+ architecture. It was previously only available in the 7 Series architecture. This is where the "7" in their name "Spartan 7 FPGA" comes from.

The 7 Series FPGAs are 28nm devices built using TSMC’s 28nm high-performance/low power (HPL) process with a logic block structure that is optimized for lower power consumption with as little as possible impact to performance as possible. This is the core of how Spartan 7 FPGAs were able to achieve its desirable optimization of performance per watt.

AMD UltraScale FPGAs also utilize TSMC technology with 20nm transistors to achieve faster clock speeds and high logic densities for applications that needed that performance boost past what the 28nm 7 Series FPGAs could offer.

Then finally, AMD UltraScale+ FPGAs are built using TSMC’s 16nm FinFET process which increased the overall speed of the device by 50% over the 20nm UltraScale FPGA parts while also consuming 60% less power running at the same clock speed.

So with this very brief dip into the differences between the physical architecture types, it becomes more obvious why the Spartan UltraScale+ FPGA complements the AMD FPGA portfolio so nicely, especially since the 20nm UltraScale FPGA is only available for the AMD Kintex and AMD Virtex device families. This is most likely due to the fact of how rapidly TSMC evolved heir technology. They brought both the 16nm and 20nm technologies into production in 2013/2014, so it appears that the UltraScale and UltraScale+ FPGAs evolved along the same timeline.

For the Spartan FPGA family specifically, the jump from a 28nm device to a 16nm device offers quite the performance boost for edge computing applications that require low power and a smaller package, but really needed the performance and speed boost.

CLBs in AMD UltraScale™/UltraScale+™ FPGAs vs 7 Series FPGAs

The Configurable Logic Block or CLB of an FPGA is the core of what makes up its fabric or "programmable logic", as it is referred to in AMD documentation. CLBs are how these FPGAs implement general purpose combinatorial and sequential circuits.

Both CLBs in both 7 Series FPGAs and UltraScale/UltraScale+ FPGAs contain real 6-input look-up table (LUT) capability with a dual LUT5 (5-input LUT) option. This means the LUTs can be configured as either one 6-input LUT with one output, or as two 5-input LUTs with separate outputs but common inputs.

Both the 7 Series FPGA and UltraScale/UltraScale+ FPGA CLBs contain distributed memory and shift register logic (SRL) ability, dedicated high-speed carry logic for arithmetic functions, wide multiplexers for efficient utilization, and 8 LUTs with 16 flip-flops per slice.

Where the CLBs in UltraScale/UltraScale+ FPGAs start to differ is that they contain dedicated storage elements that can be configured as flip-flops or latches with flexible control signals. This means that the second flip-flop that each LUT is associated with also has a dedicated input so it can be accessed simultaneously.

This means the same design can fit more compactly/densely (ie - take up less space/resources in programmable logic) on an UltraScale/UltraScale+ device as compared to a 7 Series device (see experimental proof here starting on slide 11).

Finally, the distributed RAM within the slices of the CLBs UltraScale/UltraScale+ FPGAs can store up to 512 bits of data each, which is double that of 7 Series FPGAs which can only store a maximum of 256 bits in each CLB.

DSPs slices

Alongside the CLBs to implement general purpose combinatorial and sequential circuits, AMD FPGAs also contain dedicated digital signal processing (DSP) structures with their DSP48E slices. These slices offer dedicated multiplier and accumulator resources, and digital signal processing that would otherwise take up too much room or not be as efficient if implemented in regular CLBs.

7 Series FPGAs have DSP48E1 slices that contain a 25 × 18 two’s-complement multiplier, 48-bit accumulator, 25-bit pre-adder, single-instruction-multiple-data (SIMD) arithmetic unit (ALU), logic unit, pattern detector, and optional pipelining with dedicated buses for cascading.

AMD UltraScale/UltraScale+ FPGAs have what is basically a superset of the DSP48E1 slice with their DSP48E2 slices. The DSP48E2 slices bump up to a 27 × 18 two’s-complement multiplier, 27-bit pre-adder, the ALU can handle a fourth operand with the added W-MUX multiplier, and the capability to XOR wider X, Y, Z multipliers.

While the increase in physical size from the DSP48E1 slices to the DSP48E2 is small, the increase in multiplier size has a large impact on the FPGA's ability to support floating-point arithmetic since the relationship between bit-width and the number value a register can represent is exponential by powers of two.

Clocking architecture

While much of the advancement in the clocking architecture of the UltraScale/UltraScale+ FPGAs comes from the physical layout differences between the TSMC 16nm/20nm and 28nm technologies respectively, AMD specific elements such as Clock Management Tiles (CMTs) have been optimized over 7 Series FPGAs as well. This includes features such as CMTs having two PLLs each vs just one, UltraScale architecture clock regions have a rectangular shape with a fixed width and height and are organized in tiles (compared to spanning half the horizontal device length in 7 Series FPGAs), and clock capable pins (CC) have been replaced by global clock pins (GC).

AMD Spartan UltraScale+ devices in particular add one more additional feature even compared to the rest of the UltraScale+ FPGAs. The CMTs in the Spartan UltraScale+ FPGAs that are adjacent to the integrated memory controller (LPDDRMC) and XP5IO have enhanced PLLs (PLLXP) with reserved ports for the LPDDRMC.

This means that the LPDDRMC and XP5IO have not only PLLs dedicated to them in the silicon of the Spartan UltraScale+ FPGA, but are optimized to run as fast as possible in the 16nm technology with their guaranteed adjacent physical location that cannot be impacted by the way the rest of the design is routed in the chip. This helps reduce issues with large designs potentially causing timing issues with the LPDDRMC when it being routed in the Spartan UltraScale+ FPGA by the AMD Vivado™ Design Suite tools.

GTH transceiver in AMD Spartan™ UltraScale+™ FPGAs

Another big difference the Spartan UltraScale+ FPGA offers compared to its 7 Series FPGA counterpart is the addition of up to eight gigabit (GTH) transceivers running at 16.3 Gbps.

Similar to the way that the DSP48 slices provide optimized performance for specialized applications as compared to implementation in regular CLBs, the GTH transceivers in AMD UltraScale™/UltraScale+ FPGAs are dedicated structures that are power-efficient transceivers supporting line rates from 500 Mbps to 16.375 Gbps. The GTH transceivers are highly configurable to support various protocol standards such as JESD204, PCIe, SFF-8431, Gigabit Ethernet, SATA, etc.

XP5IO I/O interface

While the list of differences between UltraScale+ FPGAs and 7 Series FPGAs could continue on, I am obviously focusing on the standout differences between Spartan UltraScale+ FPGAs and Spartan 7 FPGAs specifically in this article. And the biggest one has to be the addition of the brand new XP5IO I/O interface, which is a PHY to support high-performance interfaces like LPDDR5 and MIPI D-PHY.

At the time of writing, this new XP5IO I/O interface is only available in the Spartan UltraScale+ FPGAs in the cost-optimized portfolio. An XP5IO I/O bank contains 11 PHY nibbles where each nibble contains six NIBBLESLICEs that transmit/receive data from 6 individual I/O pins.

That means there are 66 of these individual I/O pins per XP5IO bank, and according to the product selection guide on the AMD website (XMP100), the Spartan UltraScale+ devices that have this XP5IO interface have 132 single-ended XP5IO pins, which would be a total of 2 XP5IO banks.

This XP5IO interface is basically a specialized version of the GTH transceiver tailored to the needs of LPDDR5 and MIPI D-PHY. I say this because it's another specialized part of the FPGA silicon optimized for high-speed data transfer as a more optimized way to get data into the programmable logic for processing the same way the GTH transceiver is optimized to handle high-speed interfaces such as PCIe and JESD204.

While the fabric/programmable logic is running at 300MHz or less, data can be pipelined to speed up the overall processing time, whereas an I/O pin can become a bottleneck because it's a single point of entry that's at the mercy of the silicon structure it's feeding into.

Each of these PHY nibbles are made up of six NIBBLESLICEs that contain a serializer, deserializer, I/O delays, and a receiver FIFO. The NIBBLESLICE is connected directly to the FPGA package pin so that pin is only available to the programmable logic via the XP5IO interface.

And as I touched on in the Clock Architecture section of this article, the Spartan UltraScale+ FPGA has dedicated PLLs that are physically adjacent to these XP5IO banks in order to meet the clock speeds LPDDR5 and MIPI D-PHY will need to achieve 4200 Mbps and 3200 Mbps respectively.

AMD Spartan™ UltraScale+™ FPGA security features

The new AMD Spartan UltraScale+ FPGAs feature cutting-edge security capabilities that distinguish them from other FPGAs in the cost-optimized portfolio. In UltraScale architecture FPGAs, the user bitstream configures the customized logic, which is stored in volatile SRAM-type internal latches. Consequently, the bitstream must be reloaded from non-volatile memory each time the device is powered on, creating a potential vulnerability where the custom design could be intercepted or replaced by an adversary.

To mitigate this risk, all UltraScale architecture FPGAs provide security features for encryption/decryption and optional authentication. The Spartan UltraScale+ FPGAs features secure boot capabilities, utilizing Post-Quantum Cryptography (PQC) algorithms approved by NIST.

The PQC algorithms are notable because they render the Spartan UltraScale+ FPGAs greater immunity to quantum computer brute-force attacks. This feature is a new addition to offerings from AMD, as the AMD Zynq™ UltraScale+ MPSoC and RFSoC devices previously relied on RSA-4096 asymmetric authentication with SHA-3/384.

Additionally, the Spartan UltraScale+ FPGAs employ a physically unclonable function (PUF). PUFs are used to create a “digital fingerprint” which can be used for secure external storage, black key storage, key derivation functions, and unique ID generation. Combined with true random number generators (TRNG) for secure key generation, these features make the Spartan UltraScale+ FPGAs an excellent choice for applications where security is a primary concern in the cost-optimized portfolio.

Final thoughts

In conclusion, the AMD Spartan UltraScale+ FPGA is a bigger launch than it may seem at first glance. Between filling the large hole of the Spartan device family not being available in 16nm and the addition of this new XP5IO interface, it’s on par with the addition of the RFSoCs that introduced the RF ADC and DAC tiles built into programmable logic. It also pulls some of the features previously only available in the AMD Versal™ device catalog into the cost-optimized portfolio such as the XP5IO I/O interface and more advanced security features.

AMD does have a development board for the AMD Spartan™ UltraScale+™ FPGA in the works that's currently slated to be released later this year, so I'll be curious to see what it looks like.

AMD sponsored this project. The opinions expressed in this project are those of Whitney Knitter. All opinions are provided by Whitney Knitter and have not been independently verified by AMD. Performance benefits are impacted by a variety of variables. Results herein are specific to Whitney Knitter and may not be typical. AMD, the AMD Arrow logo, Artix, Kintex, Spartan, UltraScale, UltraScale+, Versal, Virtex, Vivado, Zynq, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this project are for identification purposes only and may be trademarks of their respective companies. No technology or product can be completely secure.