Alexey Frunze's SediCi PC Is a 16-bit Microcomputer on an FPGA — with a Custom-Built CPU

RISC-inspired SediCiPU 2 delivers a classic computing experience on a low-cost FPGA development board.

Alexey Frunze has released a permissively-licensed homebrew microcomputer with a difference: it implements an entirely custom 16-bit processor of his own design, the SediCiPU 2.

"The SediCi PC is a simple 16-bit PC based on the SediCiPUv2 CPU, implemented in an FPGA (initially, Sipeed Tang Nano 20K with a GOWIN FPGA (GW2AR-18))," Frunze explains of the machine, inspired by kit-form microcomputers of years gone by. "[The CPU is] running at up to 27 MHz with 4-6 clock cycles per instruction (currently, there's no pipeline). This is my first project in (System) Verilog and the code may be less idiomatic than it should be and may also have some other deficiencies."

The SediCi PC (top) runs on a custom-designed 16-bit CPU, implemented in Verilog on an FPGA, and includes color graphics and text capabilities. (📷: Alexey Frunze)

Where most microcomputer design projects take an off-the-shelf CPU like the recently-discontinued Zilog Z80 or a modern version of the MOS 6502, or choose to go big and implement a CPU in discrete logic chips, Frunze's creation uses a custom 16-bit processor of his own design — building on the earlier SediCiPU. "This non-pipelined 16-bit architecture is relatively simple and straightforward for implementation," he claims of the "mostly RISC [Reduced Instruction Set Computer] design. "In some respects it's even simpler than the earlier SediCiPU."

Back when the second-generation SediCiPU was designed, Frunze declared that "it would be nice to build a microcomputer around this, possibly using an FPGA board with a timer (for multitasking and time keeping), VGA output, keyboard input and non-volatile storage, maybe a serial port, too" — which is exactly what the SediCi PC is. The current design includes a serial terminal, LED control, push-button input, a read-only SD Card storage interface, a "VGA(ish) text and graphics" video output supporting up to 320×240 at four bits of color per pixel, and up to 80kB of RAM when implemented on the low-cost Sipped Tang Nano 20K FPGA board.

The source code for the project is available on GitHub under the permissive BSD two-clause license, with additional details available on Hackaday.io.

ghalfacree

Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.

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