13-Year-Old Nicholas Sharkey Demonstrates How Easy It Can Be to Get Started with RISC-V Design
While taking a little longer than college-level compatriots, Sharkey successfully designed a pipelined RISC-V core during the MYTH course.
Budding developer Nicholas Sharkey has demonstrated how easy it can be to get started with the free and open source RISC-V instruction set architecture (ISA), completing a course in designing a RISC-V processor care — despite being just 13 years old.
"Recently, Kunal Ghosh of VLSI System Design and I conducted our third 'Microprocessor for You in Thirty Hours' (MYTH) Workshop, where participants learn about RISC-V and build their own RISC-V CPU cores (something that’s typically done over the course of a semester or two)," explains Redwood EDA's Steve Hoover. "In addition to reaching graduate students and professionals, one of our goals with the workshop is to give students an opportunity to learn logic design earlier in their education – like, say, as a college freshman or sophomore."
"So just imagine our surprise when Nicholas introduced himself in the chat forum of our workshop. This was a real test of our goals. It was also a real testament to Nicholas’s thirst for knowledge and the outside-the-box thinking of his home-schooling parents, Rasa and Mike. Having a 13-year-old of my own, I was particularly impressed by Nicholas’s willingness to put himself out there, asking questions and joining Zoom calls (not to mention his familiarity with Linux). I’ve since learned that Nicholas has been awarded in spelling bees and math competitions and is an expert at solving the Rubik’s Cube. Somehow, I’m not surprised."
Having worked beyond the end of the 30-hour course, Sharkey proved up to the challenge — completing the entire course, right through to the fifth day in which pipelining is added to the core design. Says Hoover, "That’s a bit hard-core for a 13-year-old, right? Having reviewed his work and discussed it with him, I’m happy to say that Nicholas has indeed successfully completed his 5-stage pipelined RISC-V CPU core and will be getting his certificate soon!
"When I asked about his experience, he responded (perhaps with a bit of parental oversight) 'I enjoyed the challenge very much, and it has gotten me excited about RISC-V and digital design.' He also expressed his gratitude to Shivam Potdar and the rest of the MYTH Workshop crew."
More details on Sharkey's work can be found on the RISC-V Foundation blog, while details of the RISC-V MYTH workshop can be found on the VLSI System Design website.