Interested in implementing artificial intelligence in your next design? Looking to broaden your understanding of designing with Xilinx’s latest Zynq UltraScale+ MPSoC? Want to shorten your prototype development efforts using Python and PYNQ? Hackster.io and Avnet are pleased to introduce six on-line training courses that will equip you with the knowledge and skills needed for your next Zynq UltraScale+ design.

In this 3-course technical training bundle you will learn the fundamentals of developing software applications, building a custom hardware platform, and running the PetaLinux tools to build embedded Linux for Ultra96. Each course takes about 6-7 hours to complete. This single online bundle gives you access to all three courses at a pace you desire.

The advanced courses allow you to dive deeper into application specific areas including SDSoC, Artificial Intelligence, and Python/PYNQ. Each advanced course takes approximately 12-14 hours to complete and can be purchased individually.

Each training course is composed of short 15-20 minute presentations followed by a 30-minute hands-on lab. The labs are built on Avnet’s Ultra96 - a low-cost, easy to use platform based on the Xilinx Zynq UltraScale+ MPSoC. All the labs support both the Ultra96-V1 and V2. Additional hardware that is required beyond the Ultra96 kit is highlighted below.

In this 3-course technical training bundle you will learn the fundamentals of developing software applications, building a custom hardware platform, and running the PetaLinux tools to build embedded Linux for Ultra96. Each course takes about 6-7 hours to complete. This single online bundle gives you access to all three introductory courses at a pace you desire.

This course explores the fundamental concepts of the Xilinx Software Development Kit (SDK). Using a pre-built hardware platform, you will learn how to navigate the SDK environment and develop some basic C-code examples for the Ultra96 / Ultra96-V2 board.

Connect the SDK to hardware for execution and debug

Utlilize a peripheral interrupt to show real-time software response

Learn to use an external sensor module

Explore how to import hardware into your Xilinx SDK environment

Introduction to the Xilinx SDK

This course will teach you how to develop a Zynq UltraScale+ MPSoC hardware platform using the Xilinx Vivado tools while also learning ZU+ architecture. Vivado is used to configure the processing system parameters, including clocking, memory interface, and peripherals. Vivado is also used to develop custom hardware in the programmable logic. Build a working hardware platform that runs your code on the Ultra96 / Ultra96-V2 board.

Introduction to the Zynq UltraScale + MPSoC Architecture, including the Arm Cortex™-A53 processor

Utilize the Xilinx embedded systems tool to:

• Design a Zynq UltraScale + MPSoC system
• Add Xilinx and custom IP
• Run software applications to test the IP
• Debug an embedded system

Introduction to the Zynq UltraScale + MPSoC development flow with
Vivado's IP Integrator

Prerequisites:

• Developing Zynq UltraScale + MPSoC Software course or applicable experience 

From within an Ubuntu OS running within a virtual machine, learn how to install PetaLinux and build embedded Linux targeting Ultra96 or Ultra96-V2. In the hands-on labs learn about Yocto and PetaLinux tools to import your own FPGA hardware design, integrate user space applications, and configure/customize PetaLinux.

Import existing Vivado hardware designs into PetaLinux

Add custom applications into PetaLinux

Build, customize, and configure PetaLinux for Ultra96

Prerequisites: 

• Developing Zynq UltraScale + MPSoC Software course or applicable experience 

Includes all 3 courses below

The advanced courses allow you to dive deeper into application-specific areas including SDSoC, Artificial Intelligence, and Python/PYNQ. Each advanced course takes approximately 12-14 hours to complete and can be purchased individually. 

Using proven flows for SDSoC, you will learn to navigate the SDSoC tool. On the first day, through hands-on labs, we will create a design for a provided platform and then create a platform for the Avnet Ultra96. You will see how to accelerate an algorithm during the course lab. On the second day, a similar workflow is taken. This time focusing on PetaLinux integration, while leveraging the knowledge we built from day one. The overall experience should give you the background needed to assist in developing custom platforms with custom algorithms, accelerated by SDSoC.

Build a bare metal platform from scratch

Enable and test a PetaLinux BSP running on the Ultra96 Board

Introduction to the design concepts and problem-solving techniques of SDSoC

Test the platform using a simple matrix multiplier example

Prerequisites: 

• A working knowledge of Xilinx Vivado, SDK, and PetaLinux design tools OR attendance at our other three fundamentals courses

• Experience with the Vivado 2018.3 tools is recommended but not required.  

Deep learning achieves human-like accuracy for many tasks considered algorithmically unsolvable with traditional machine learning. It is frequently used to develop applications such as face recognition, automated driving, and image classification.

Introduction to Deep Learning with Xilinx SoCs is a technical training course that provides a hands-on introduction to deep learning. The Xilinx Edge AI Inference solution is used to deploy the DNN for inference on the Xilinx MPSoC (Ultra96).

Prerequisites: 

• Deep Learning Onramp (MathWorks)

• PetaLinux Tools for Ultra96 Development or applicable experience 

Overview of Xilinx's AI Inference solutions, from cloud to edge

Deep dive into the development flow for Xilinx edge AI platforms

Quantize, compile, and deploy DNNs to the Ultra96

Take Python to the next level with PYNQ and the Avnet Ultra96 hardware platform. PYNQ is an open source Python productivity framework for Xilinx MPSoC that comes integrated with AArch64 Linux based on Ubuntu 18.04 LTS. Ultra96 is a 96Boards certified, palm of your hand computing platform designed around the high-performance Xilinx MPSoC ZU3EG. The ZU3EG has 6 Arm™ CPUs, display port, multiple peripherals and programmable logic.

Prerequisites: 

• Some knowledge of Python 3 is necessary
• General Linux experience, Xilinx hardware design skills and understanding of C programming is recommended but not required.
  

Develop applications for Ultra96 with a web browser based IDE: Jupyter Labs

Re-use open source based projects with Ultra96

Write custom drivers completely in Python to interface with Xilinx programmable logic

Control hardware with Python

Accelerate Python with hardware

Create living-code documents with Jupyter Notebooks

Working examples will include: Machine learning image classification, hardware accelerated OpenCV and more...

To complete the labs for each course, the following Avnet hardware is required:

AES-ACC-U96-ME-SK

Required for introductory courses only

AES-ACC-U96-JTAG

Required for all courses except advanced Ultra96 PYNQ course

AES-ULTRA96-G or AES-ULTRA96-V2-G

Includes a 16GB microSD card + voucher to license required Xilinx development tools

AES-ACC-U96-4APWR

Laptop with Xilinx Vivado Design Suite 2018.3 installed

Micro-USB cable

Recommended cameras include Logitech BRIO, Logitech C920 and Logitech C270

Required for Introduction to Deep Learning Course ONLY

USB Camera

USB-to-SD card reader

Required for all courses except the Ultra96 PYNQ course

Required for introductory courses only

4 Amp power supply required when using the click mezzanine. Using a 2 Amp version risks damage to your power supply.

Senior Design Engineer, Avnet 

Dan Rozwood’s career as a Systems Design Engineer includes eleven years working in FPGA development and five years supporting Avnet’s SOM portfolio, based on the Zynq and Zynq UltraScale+ devices. He was an early adopter of SDSoC and has since been pushing the limits of this system flow ideology for customized accelerator development. Working with Xilinx, Dan has created a multitude of new training and work flow designs to help developers leverage the power of customized accelerators using the System On Chip (SoC) platforms available from Xilinx.

Adam Taylor is the author of the MicroZed Chronicles which, over 5 years, 270 plus articles and 20 million plus views has taught engineers how to use the Zynq, Zynq MPSoC and Xilinx FPGAs. When he is not teaching or writing about FPGA /SoC development Adam develops FPGA based solutions for a range of applications including RADAR, nuclear reactors, satellites, cryptography and image processing. Adam is a Chartered Engineer, Fellow of the Institute of Engineering and Technology and Visiting Professor of embedded systems at the University of Lincoln, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training

Owner, Adiuvo Engineering and Training LTD

Senior Design Engineer, Avnet 

Fred Kellerman has been developing with the Ultra96 development board since its inception. In the fall of 2018, Xilinx, Avnet and the Open Source community turned up the fun factor and productivity dial by putting together a Linux AArch64 Ubuntu rootfs that included the PYNQ framework for Ultra96. PYNQ is Python for Zynq. Zynq is Xilinx’s MPSoC chip that combines ARM CPUs with programmable logic. Fred is now addicted to PYNQ and likes to share his new obsession with others. Fred has professionally designed real-time embedded systems. He speaks C/C++/VHDL and Python. He has also developed signal processing applications with FPGAs and DSPs. He holds BSEE and MSEE degrees from RIT where he also occasionally teaches a graduate

course in digital radio communication systems.

Senior Design Engineer, Avnet

Mario Bergeron is a Systems Design Engineer for Avnet, specializing in video, image and digital signal processing. Mario has a Bachelors of Science degree in Computer Engineering from Université Laval in Québec City. He started his career as an ASIC designer, and has since then accumulated over 25 years of DSP and FPGA based embedded design experience. Present activities include video and imaging development platforms, reference designs, and customer training.

Private forum where you can connect with the instructors and other attendees

PDF documentation of each lab performed during this course + resources for further learning

A personalized Certificate of Completion in your inbox that can be used for advancing your career or bragging to your friends

Step-by-step getting started guide to help you set up any required hardware or software used in the labs

Course instruction and labs taught by industry professionals

The Ultra96 Introductory technical training courses are on-demand and can be accessed from your Hackster account as soon as your purchase is complete. The Ultra96 Advanced courses are coming soon. Sign up here to be notified when they are available for purchase.

If you are unsatisfied with your purchase, please contact us at help@hackster.io within 30 days of your purchase to request a refund. Some restrictions may apply. 

There are no prerequisites for the Zynq Ultrascale + MPSoC Software course, but we do recommend you have prior knowledge of Zynq Ultrascale + MPSoC Software when attending the hardware and PetaLinux courses. 

Prerequisites for each advanced course can be found under the course objectives above.

No, the online courses are on-demand and can be purchased and watched at any time on Hackster.io

In order to participate in the labs you will need a computer with Xilinx Vivado Design Suite 2018.3 installed, an Ultra96 board, Ultra96 JTAG Pod, power supply, and click mezzanine board (introductory courses only). See recommended hardware section above for more details and links to purchase.

By 

If you have any questions regarding the Ultra96 Introductory Bundle or Ultra96 Advanced courses, please contact us at help@hackster.io.

Integrating Sensors on Ultra96 with PetaLinux 2018.3

Zynq UltraScale + MPSoC Software

Zynq UltraScale + MPSoC Hardware

Intro to Deep Learning with Xilinx SoCs

Turbocharge Python with Ultra96 PYNQ

Getting Started with Xilinx SDSoC 2018.3