ILA Debugging on Artix- 7 FPGA

ILA - Integrator Logic Analyzer

It is an IP provided by Xilinx for debugging the circuits inside the FPGA Hardware.

It comes handy for debugging various pieces of information which cannot be seen just in simulation.

• Binary Counter IP - This IP (Intellectual Property) is also Provided by Xilinx.
• It could be used for generating various patterns of 1's and 0's in Up and Down Count Direction.

For Learning What is Binary Counter IP is Click here

Let's Get to Experimentation

• Start VIVADO and give a project name

• Click Next

• Go to Boards Section, Select your FPGA

if you do not see your FPGA Board in this section then download the board files from Digilent for Xilinx FPGAs from here and for EDGE ARTIX-A7 from here

After Downloading extract those files in

F:\xilinx\Vivado\2019.2\data\boards\board_files

In case you had installed VITIS and VIVADO it will be lying somewhere around here -:

E:\VITIS_2020.2\Vivado\2022.2\data\boards\board_files

• Create Block Design from the Highlighted Section

• Give a name of the Block Design then Click-OK

• GO to Windows section and Click on Boards

• You would now be able to see the Board files section
• Right Click System Clock and then Click on Connect Board Component

• By default leave it as only one Clock being used

• By Now you'd be able to see the clock wizard in Diagram Section
• Double Click on Clock Wizard IP in Block Design

• Now Go to output Clocks and here you can have any frequency for clk_out1

which would be used for binary counter and ILA

• Now Click on + in Block Diagram and Search Binary Counter

• Configure Binary Counter IP as the Following.

• Configuring Control Section

• Now Search for ILA in block design by clicking on +
• Double Click on ILA (Integrated Logic Analyzer)

• Configure the ILA as the following by double clicking.

• Go to Probe Section

• Now Right Click on Binary Counter's Pin CE and make it external.

• Right click on Clock Wizard Reset Pin and Make it External.

• Double Click on Clocking Wizard IP

and Untick the Locked Section

Connect All three IPs like the Following then click on Regenerate the Layout

• Now Validate the Design for making sure there isn't any errors in Block Design connection.

• Go to Sources,
• At the very top section under edit section click on save section as highlighted in Following, it will save the Block Design
• Then right click on the block Design project file in sources and click on
• Generate the output products

• SelectGlobal

• Right Click on Project file and Select Create HDL Wrapper
• Then Click on Let Vivado manage wrapper and auto update

• Run Synthesis

• Open Synthesized Design
• From Layout Section Click on I/O Planning

• You would be able to see I/O Ports Section

• Check pin Voltage section for your FPGA Board, in Most Cases it should be LVCMOS33

• I have Used one of the switches for CE pin on FPGA and Gave the pin location in Package pin section.
• Now Save Constraints as highlighted section

• Give an Appropriate name to XDC file.

• Click ok

• Click on Generate Bitstream

• You would be able to see the implemented design schematic after clicking on Open Implemented Design

• Open Hardware manager then click on Program the board.
• Make sure the CE pin was at active low at the time of Programming.
• then after programming you can assert(Active-high) the CE pin.

I hope you learnt something Today :-)

Happy Learning :-)